diff --git a/src/coreboot/default.nix b/src/coreboot/default.nix index e00778c..e54366b 100644 --- a/src/coreboot/default.nix +++ b/src/coreboot/default.nix @@ -1,4 +1,5 @@ -{ nixpkgsOnBuildForBuild +{ lib +, nixpkgsOnBuildForBuild , coreboot-toolchain ? throw "missing" , payload ? throw "you must provide a coreboot payload (Linux kernel image or FIT)" , fmap ? throw "you must provide an FMAP (flash chip partition table)" @@ -6,8 +7,14 @@ , initramfs_image # path to the initramfs `cpio` archive , iasl ? null # a specific iasl to use, if needed , console_loglevel ? "6" # 8=SPEW, 7=DEBUG, 6=INFO + +# Can be null or an integer (0, 1, 2, ...); note: the mapping from +# these integers to ttyS* values is occasionally not the identity +# map. +, uart-for-console ? throw "you must provide uart-for-console" , linux-command-line }: + let version = "4.9"; inherit (nixpkgsOnBuildForBuild) stdenv lib git python3 ncurses fetchgit; @@ -24,8 +31,8 @@ stdenv.mkDerivation { inherit version; passthru = { inherit src fmap; }; - inherit src; + inherit src; patches = let inherit (nixpkgsOnBuildForBuild) fetchpatch; in [ (fetchpatch { # Makefile.inc: Use `define` for cbfs-files-processor-defconfig @@ -63,6 +70,12 @@ stdenv.mkDerivation { ./patches/0020-use_fallback-kgpe-d16-implement-using-nvram-with-cmo.patch ./patches/0021-am1i-omit-amdfw.rom-completely-it-has-broken-address.patch ./patches/0022-kgpe-d16-disable-sanitize_cmos-it-causes-too-many-pr.patch + ./patches/0023-kgpe-d16-disable-TPM.patch + ./patches/0024-amd-sb700-early_setup.c-select-console-properly.patch + ./patches/0025-southbridge-amd-sb700-lpc.c-set-SPI-flash-aperture-t.patch + ./patches/0001-mainboard-asus-kgpe-d16-romstage.c-support-console-o.patch + ./patches/0002-southbridge-amd-sb700-lpc.c-leave-LPC-timeout-mechan.patch + ./patches/0003-treewide-reduce-many-messages-to-BIOS_SPEW.patch # the next two patches are required in order for the third patch to apply properly (fetchpatch { @@ -98,7 +111,7 @@ stdenv.mkDerivation { enableParallelBuilding = false; # does not work # FIXME: use the nixpkgs `kernel/manual-config.nix` machinery here - configurePhase = '' + configurePhase = assert uart-for-console == null || lib.isInt uart-for-console; '' runHook preConfigure cp ${config} .config chmod +w .config @@ -113,6 +126,9 @@ stdenv.mkDerivation { echo 'CONFIG_PAYLOAD_FILE="${payload}"' >> .config sed -i 's/^CONFIG_LINUX_INITRD=.*//' .config echo 'CONFIG_LINUX_INITRD="${initramfs_image}"' >> .config + sed -i 's/^CONFIG_UART_FOR_CONSOLE=.*//' .config + '' + lib.optionalString (uart-for-console != null) '' + echo 'CONFIG_UART_FOR_CONSOLE=${builtins.toString uart-for-console}"' >> .config '' + lib.optionalString (iasl != null) '' echo CONFIG_ANY_TOOLCHAIN=y >> .config '' + '' diff --git a/src/coreboot/patches/0001-mainboard-asus-kgpe-d16-romstage.c-support-console-o.patch b/src/coreboot/patches/0001-mainboard-asus-kgpe-d16-romstage.c-support-console-o.patch new file mode 100644 index 0000000..45b1117 --- /dev/null +++ b/src/coreboot/patches/0001-mainboard-asus-kgpe-d16-romstage.c-support-console-o.patch @@ -0,0 +1,38 @@ +From f960a8ecf4e84d6f759b38cd15890c1ab1900573 Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Thu, 13 Apr 2023 00:30:35 -0700 +Subject: [PATCH 1/3] mainboard/asus/kgpe-d16/romstage.c: support console on + ttyS1 + +Currently the romstage serial console initialization always +initializes SP1 (the DB9 header on the back of the motherboard). +Changing UART_FOR_CONSOLE simply causes the romstage to map the same +serial port at a different address (0x2f8). + +This commit accounts for UART_FOR_CONSOLE (and its effect on +TTYS0_BASE) correctly: if UART_FOR_CONSOLE is changed from 0 to 1, +the romstage console output will be printed on the SP2 header (the +IDC ribbon header on the motherboard). +--- + src/mainboard/asus/kgpe-d16/romstage.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c +index 9d84fe059a..e5599607d7 100644 +--- a/src/mainboard/asus/kgpe-d16/romstage.c ++++ b/src/mainboard/asus/kgpe-d16/romstage.c +@@ -514,7 +514,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B); + + /* Initialize early serial */ ++#if CONFIG_TTYS0_BASE == 0x3f8 + winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE); ++#elif CONFIG_TTYS0_BASE == 0x2f8 ++ winbond_enable_serial(SERIAL_1_DEV, CONFIG_TTYS0_BASE); ++#endif + console_init(); + + /* Disable LPC legacy DMA support to prevent lockup */ +-- +2.39.1 + diff --git a/src/coreboot/patches/0002-southbridge-amd-sb700-lpc.c-leave-LPC-timeout-mechan.patch b/src/coreboot/patches/0002-southbridge-amd-sb700-lpc.c-leave-LPC-timeout-mechan.patch new file mode 100644 index 0000000..2147c10 --- /dev/null +++ b/src/coreboot/patches/0002-southbridge-amd-sb700-lpc.c-leave-LPC-timeout-mechan.patch @@ -0,0 +1,33 @@ +From 212e744d043c4d448d10931631699a71bf69f472 Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Thu, 13 Apr 2023 00:34:25 -0700 +Subject: [PATCH 2/3] southbridge/amd/sb700/lpc.c: leave LPC timeout mechanism + enabled + +I've been experiencing boot hangs during PNP enumeration of the LPC +bus. The southbridge chip comes with a mechanism to prevent +unresponsive/syncflooding LPC devices from wedging the system; let's +use it. +--- + src/southbridge/amd/sb700/lpc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c +index 47d588012a..1fbd498732 100644 +--- a/src/southbridge/amd/sb700/lpc.c ++++ b/src/southbridge/amd/sb700/lpc.c +@@ -59,9 +59,9 @@ static void lpc_init(struct device *dev) + pci_write_config8(dev, 0x40, byte); + } + +- /* Disable the timeout mechanism on LPC */ ++ /* Enable the timeout mechanism on LPC ("Sync Timeout Counter Enable") */ + byte = pci_read_config8(dev, 0x48); +- byte &= ~(1 << 7); ++ byte |= (1 << 7); + pci_write_config8(dev, 0x48, byte); + + /* Disable LPC MSI Capability */ +-- +2.39.1 + diff --git a/src/coreboot/patches/0003-treewide-reduce-many-messages-to-BIOS_SPEW.patch b/src/coreboot/patches/0003-treewide-reduce-many-messages-to-BIOS_SPEW.patch new file mode 100644 index 0000000..ee7bc0e --- /dev/null +++ b/src/coreboot/patches/0003-treewide-reduce-many-messages-to-BIOS_SPEW.patch @@ -0,0 +1,151 @@ +From 7899c0aea9891384df5353eedbe1a23c4c4f428d Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Thu, 13 Apr 2023 00:35:26 -0700 +Subject: [PATCH 3/3] treewide: reduce many messages to BIOS_SPEW + +--- + src/commonlib/cbfs.c | 6 ++++-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++-- + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 20 ++++++++++---------- + 3 files changed, 16 insertions(+), 14 deletions(-) + +diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c +index aa83ff759d..01cbde5dc8 100644 +--- a/src/commonlib/cbfs.c ++++ b/src/commonlib/cbfs.c +@@ -174,7 +174,9 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, + { + struct cbfsf *prev; + ++#if 0 + LOG("Locating '%s'\n", name); ++#endif + + prev = NULL; + +@@ -225,11 +227,11 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, + if (*type == 0) + *type = ftype; + } +- ++#if 0 + LOG("Found @ offset %zx size %zx\n", + rdev_relative_offset(cbfs, &fh->metadata), + region_device_sz(&fh->data)); +- ++#endif + /* Success. */ + return 0; + } +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +index 34d1c1f73a..1d843b75dc 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +@@ -4016,12 +4016,12 @@ void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, + do { + dword = Get_NB32(dev, 0x110); + +- printk(BIOS_DEBUG, "."); ++ printk(BIOS_SPEW, "."); + } while (dword & (1 << MemClrBusy)); + + printk(BIOS_DEBUG, "\n"); + do { +- printk(BIOS_DEBUG, "."); ++ printk(BIOS_SPEW, "."); + dword = Get_NB32(dev, 0x110); + } while (!(dword & (1 << Dr_MemClrStatus))); + printk(BIOS_DEBUG, "\n"); +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +index 3ca1a98abb..3bbf93bac3 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +@@ -282,7 +282,7 @@ uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, ui + } + } + +- printk(BIOS_INFO, "DIMM %d RttWr: %01x\n", dimm, term); ++ printk(BIOS_SPEW, "DIMM %d RttWr: %01x\n", dimm, term); + + return term; + } +@@ -680,7 +680,7 @@ uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, u + } + } + +- printk(BIOS_INFO, "DIMM %d RttNom: %01x\n", dimm, term); ++ printk(BIOS_SPEW, "DIMM %d RttNom: %01x\n", dimm, term); + return term; + } + +@@ -689,13 +689,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct) + u32 dev = pDCTstat->dev_dct; + u32 val; + +- printk(BIOS_DEBUG, "%s: Start\n", __func__); ++ printk(BIOS_SPEW, "%s: Start\n", __func__); + + do { + val = Get_NB32_DCT(dev, dct, 0x98); + } while (!(val & (1 << DctAccessDone))); + +- printk(BIOS_DEBUG, "%s: Done\n", __func__); ++ printk(BIOS_SPEW, "%s: Done\n", __func__); + } + + static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct) +@@ -740,7 +740,7 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS) + u32 dev = pDCTstat->dev_dct; + u32 val; + +- printk(BIOS_DEBUG, "%s: Start\n", __func__); ++ printk(BIOS_SPEW, "%s: Start\n", __func__); + + val = Get_NB32_DCT(dev, dct, 0x7c); + val &= ~0x00ffffff; +@@ -752,7 +752,7 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS) + val = Get_NB32_DCT(dev, dct, 0x7c); + } while (val & (1 << SendMrsCmd)); + +- printk(BIOS_DEBUG, "%s: Done\n", __func__); ++ printk(BIOS_SPEW, "%s: Done\n", __func__); + } + + u32 mct_MR2(struct MCTStatStruc *pMCTstat, +@@ -1079,7 +1079,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) + u32 dev = pDCTstat->dev_dct; + u32 dword; + +- printk(BIOS_DEBUG, "%s: Start\n", __func__); ++ printk(BIOS_SPEW, "%s: Start\n", __func__); + + /*1.Program MrsAddress[10]=1 + 2.Set SendZQCmd = 1 +@@ -1098,7 +1098,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) + /* 4.Wait 512 MEMCLKs */ + mct_Wait(300); + +- printk(BIOS_DEBUG, "%s: Done\n", __func__); ++ printk(BIOS_SPEW, "%s: Done\n", __func__); + } + + void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, +@@ -1108,7 +1108,7 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, + u32 dword; + u32 dev = pDCTstat->dev_dct; + +- printk(BIOS_DEBUG, "%s: Start\n", __func__); ++ printk(BIOS_SPEW, "%s: Start\n", __func__); + + if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { + /* 3.Program F2x[1,0]7C[EnDramInit]=1 */ +@@ -1206,5 +1206,5 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, + mct_DCTAccessDone(pDCTstat, dct); + } + +- printk(BIOS_DEBUG, "%s: Done\n", __func__); ++ printk(BIOS_SPEW, "%s: Done\n", __func__); + } +-- +2.39.1 + diff --git a/src/coreboot/patches/0023-kgpe-d16-disable-TPM.patch b/src/coreboot/patches/0023-kgpe-d16-disable-TPM.patch new file mode 100644 index 0000000..908afe4 --- /dev/null +++ b/src/coreboot/patches/0023-kgpe-d16-disable-TPM.patch @@ -0,0 +1,42 @@ +From 329f789c8cb0a1a6d4ce5cc5a2d7fa5ff9c6d95b Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Wed, 12 Apr 2023 23:36:31 -0700 +Subject: [PATCH] kgpe-d16: disable TPM + +I have never heard of anybody using a TPM on this board, and the +fewer things we need to deal with during the somewhat-flaky LPC +init, the better. +--- + src/mainboard/asus/kgpe-d16/Kconfig | 1 - + src/mainboard/asus/kgpe-d16/devicetree.cb | 3 --- + 2 files changed, 4 deletions(-) + +diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig +index d87d9269cc..c6b2de3ab9 100644 +--- a/src/mainboard/asus/kgpe-d16/Kconfig ++++ b/src/mainboard/asus/kgpe-d16/Kconfig +@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS + select BOARD_ROMSIZE_KB_2048 + select ENABLE_APIC_EXT_ID + select SPI_FLASH +- select MAINBOARD_HAS_LPC_TPM + select HAVE_ACPI_RESUME + select DRIVERS_I2C_W83795 + select DRIVERS_ASPEED_AST2050 +diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb +index 9039f6dea2..ff2023ddd0 100644 +--- a/src/mainboard/asus/kgpe-d16/devicetree.cb ++++ b/src/mainboard/asus/kgpe-d16/devicetree.cb +@@ -214,9 +214,6 @@ chip northbridge/amd/amdfam10/root_complex # Root complex + device pnp 2e.d off end # VID_BUSSEL + device pnp 2e.f off end # GPIO_PP_OD + end +- chip drivers/pc80/tpm +- device pnp 4e.0 on end # TPM module +- end + end + device pci 14.4 on # Bridge + device pci 1.0 on end # VGA +-- +2.39.1 + diff --git a/src/coreboot/patches/0024-amd-sb700-early_setup.c-select-console-properly.patch b/src/coreboot/patches/0024-amd-sb700-early_setup.c-select-console-properly.patch new file mode 100644 index 0000000..4ca3119 --- /dev/null +++ b/src/coreboot/patches/0024-amd-sb700-early_setup.c-select-console-properly.patch @@ -0,0 +1,38 @@ +From 931a025c1032bb00b084210c6b5ad0a4235ebfdb Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Thu, 13 Apr 2023 00:07:56 -0700 +Subject: [PATCH] amd/sb700/early_setup.c: select console properly + +Currently, sb700/early_setup.c has this comment: + + // XXX Serial port decode on LPC is hardcoded to 0x3f8 + +... and it unconditionally sets the output enable for ttyS0, even if +ttyS1 is also enabled. As a result, if coreboot is configured to +use ttyS1 for serial output, the romstage console output will appear +on *both* consoles. + +This commit fixes that. +--- + src/southbridge/amd/sb700/early_setup.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c +index 70cf340c8e..4dfe6dd2ee 100644 +--- a/src/southbridge/amd/sb700/early_setup.c ++++ b/src/southbridge/amd/sb700/early_setup.c +@@ -160,9 +160,10 @@ void sb7xx_51xx_lpc_init(void) + + dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + /* Decode port 0x3f8-0x3ff (Serial 0) */ +- // XXX Serial port decode on LPC is hardcoded to 0x3f8 + reg8 = pci_read_config8(dev, 0x44); ++#if CONFIG_TTYS0_BASE == 0x3f8 + reg8 |= 1 << 6; ++#endif + #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) + #if CONFIG_TTYS0_BASE == 0x2f8 + reg8 |= 1 << 7; +-- +2.39.1 + diff --git a/src/coreboot/patches/0025-southbridge-amd-sb700-lpc.c-set-SPI-flash-aperture-t.patch b/src/coreboot/patches/0025-southbridge-amd-sb700-lpc.c-set-SPI-flash-aperture-t.patch new file mode 100644 index 0000000..b9f1c19 --- /dev/null +++ b/src/coreboot/patches/0025-southbridge-amd-sb700-lpc.c-set-SPI-flash-aperture-t.patch @@ -0,0 +1,30 @@ +From d3154d80bd53c5de3395ae0a50beccbc11af4a9d Mon Sep 17 00:00:00 2001 +From: Your Name +Date: Thu, 13 Apr 2023 00:19:19 -0700 +Subject: [PATCH] southbridge/amd/sb700/lpc.c: set SPI flash aperture to 16MB + +The SPI flash aperture for the southbridge chip is set to 8MB, even +when a 16MB chip is used. Let's make the aperture large enough for +the maximum size chip that this board can accomodate. +--- + src/southbridge/amd/sb700/lpc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c +index 857503a7ed..47d588012a 100644 +--- a/src/southbridge/amd/sb700/lpc.c ++++ b/src/southbridge/amd/sb700/lpc.c +@@ -98,8 +98,8 @@ static void sb700_lpc_read_resources(struct device *dev) + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); +- res->base = 0xff800000; +- res->size = 0x00800000; /* 8 MB for flash */ ++ res->base = 0xff000000; ++ res->size = 0x01000000; /* 16 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + +-- +2.39.1 +