diff --git a/src/coreboot/default.nix b/src/coreboot/default.nix
index 904cf90..5c3b226 100644
--- a/src/coreboot/default.nix
+++ b/src/coreboot/default.nix
@@ -107,6 +107,8 @@ stdenv.mkDerivation {
     ./patches/0002-kgpe-d16-do-not-enable-hw-monitor-until-kernel-boots.patch
     ./patches/0026-kgpe-d16-start-w83667hg-a-watchdog-during-romstage.patch
     ./patches/0004-kgpe-d16-romstage.c-do-a-double-reset-on-other_reset.patch
+    # does not seem necessary; kept in-tree but unapplied for future use
+    #./patches/0003-southbridge-amd-sb700-disable-two-hacks.patch
 
     # am1i patches
     ./patches/0021-am1i-omit-amdfw.rom-completely-it-has-broken-address.patch
diff --git a/src/coreboot/patches/0003-southbridge-amd-sb700-disable-two-hacks.patch b/src/coreboot/patches/0003-southbridge-amd-sb700-disable-two-hacks.patch
new file mode 100644
index 0000000..6d92781
--- /dev/null
+++ b/src/coreboot/patches/0003-southbridge-amd-sb700-disable-two-hacks.patch
@@ -0,0 +1,44 @@
+From aa5b636937bd1ce6dd9ec414ddca293f19085e31 Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Tue, 13 Jun 2023 01:16:05 -0700
+Subject: [PATCH 3/4] southbridge/amd/sb700: disable two hacks
+
+This commit disables two hacks:
+
+ - "RPR 2.26 Alter CPU reset timing", introduced by commit
+   d1b6ff80c017e671c1e2229ee0d659e491ab53f5
+
+ - "Work around system clock drift issues", introduced by commit
+   905507c3790829e8a6352d857bbad446e6c1c4e6
+
+Neither of the commits which introduced these two hacks contains any
+useful information in the commit message, nor am I able to find
+anything about altering CPU reset timing in section 2.26 of the
+SB700 "Register Programming Requirements" (RPR) document.
+---
+ src/southbridge/amd/sb700/early_setup.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
+index 4dfe6dd2ee2..21c1353c3d3 100644
+--- a/src/southbridge/amd/sb700/early_setup.c
++++ b/src/southbridge/amd/sb700/early_setup.c
+@@ -686,6 +686,7 @@ static void sb700_pmio_por_init(void)
+ 	byte |= 0xc0;
+ 	pmio_write(0xbb, byte);
+ 
++#if 0
+ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
+ 	/* RPR 2.26 Alter CPU reset timing */
+ 	byte = pmio_read(0xb2);
+@@ -698,6 +699,7 @@ static void sb700_pmio_por_init(void)
+ 	byte |= 0x1 << 7;	/* Disable 25MHz oscillator buffer */
+ 	pmio_write(0xd4, byte);
+ #endif
++#endif
+ }
+ 
+ /*
+-- 
+2.39.1
+