Prior to this commit, ownerboot had quite a lot of "magic addresses"
and flash chip layouts. This commit eliminates all of them.
All flash chip geometry is now computed from first principles and
two parameters:
1. The flash chip size
2. The number of images per chip (two means NORMAL/FALLBACK)
If (flash-chip-size / num-images) is too small, coreboot's build
process will notice this and fail.
It should be possible to build a single-image (i.e. no FALLBACK)
ownerboot for use on 8mbyte flash chips, which lets people try this
out without having to buy a new flash chip or (in the case of the
rk3399-gru-kevin laptop) doing any soldering.
This commit significantly cleans up the assembly of the initramfs by
specifying and manipulating its contents using an attrset (in { dest
= src; } form) rather than chunks of bash script.
Previously the initramfs required overriders to use a custom
`$build` environment variable as the destination for files to be
packed into an initramfs image. This commit eliminates it, so the
standard $NIX_BUILD_TOP can be used instead.
Previously ownerboot had separate `userspace` (the initramfs
contents without kernel modules) and `initramfs` (the complete
initramfs) expressions. This was done in order to allow the use of
CONFIG_INITRAMFS_SOURCE, which links an initramfs image into the
kernel itself.
I did this because I was having a hard time getting coreboot to load
a separate initrd on rk3399. I have since solved that problem, and
am now using coreboot to load an initramfs on all platforms. There
is no longer any need for this unusual separation.
This commit moves the `fmap` and `payload` arguments to `coreboot`
into the top-level scope, so they can be provided without needing to
override the `coreboot` expression.
This commit causes the coreboot payload (i.e. the Linux kernel,
initramfs, and any necessary DTBs) to be inserted into the coreboot
image as part of a separate derivation from the one which compiles
coreboot.
As a result, changing the contents of the initramfs is extremely
fast -- it can now be done without any recompilation.
As a result of this, the attribute name for the final image to be
flashed has changed from `coreboot` to `image`. The `coreboot`
attribute now builds a payloadless `coreboot.rom`.
This commit adds a coreboot patch which enables
CONFIG_USE_WATCHDOG_ON_BOOT for kgpe-d16; in upstream coreboot this
feature is found on only a few intel cpu platforms.
When enabled, this feature starts the hardware watchdog very early
in the boot process -- before PNP enumeration or DRAM
initialization. This ensures that any hangs or freezes due to
transient conditions (flakiness, temperature, electrical noise)
won't prevent the machine from eventually booting. This is very
useful for unattended servers.
On kgpe-d16 the watchdog is cancelled immediately before jumping to
the payload (i.e. Linux kernel). I found that if I left the
watchdog enabled, any attempt to use it (for example, to cancel it
or extend it) from Linux resulted in the machine resetting. Perhaps
this can be fixed, but for now I am content to simply re-enable the
watchdog from Linux rather than leaving it running.
Previously, the flashrom scripts would pass --fmap to every
invocation of flashrom, even when overwriting the entire image.
This was unnecessary, and would cause issues if the chip being
written to had a corrupted fmap table. This commit passes the
--fmap flag only when it is needed due to the -i flag being present.
Now that 6deb86f6138265a715dd005c310ad33a2e2865ff has merged
upstream in nixpkgs we can directly reference arm-trusted-firmware
as part of the nixpkgs package set. This allows to eliminate a
<nixpkgs>-style path reference.
In order to write to the chromebook embedded controller flash we
need to use Google's fork of flashrom. However for writing to the
chromebook CPU firmware flash (which is a different flash chip) we
can use mainline flashrom. So let's do that.
On x86 platforms, it is necessary to wrap the entire image in a
BIOS@0 region which marks the memory-mapped flash image as needing
SMM protection. Unfortunately this creates overlapping FMAP
regions, which flashrom cannot handle without a patch.
On arm64 platforms, the BIOS@0 region is not needed. So let's not
include it. This allows us to skip the flashrom patch on arm64.
Upstream describes this option as "Enable this option if coreboot
shall read options from the CMOS NVRAM instead of using hard-coded
values."
The RTC_BOOT_BYTE (which controls normal/fallback) indicator is
always taken from CMOS NVRAM, regardless of how this option is set.
When set to `no`, no other parts of the CMOS NVRAM are read or
written.
On KGPE-D16 I have found that USE_OPTION_TABLE=yes is frustratingly
flaky and unstable; about 1 in 20 boots will hang in the PNP device
enumeration. Apparently during SMP boot, multiple cores attempt to
access the (single) CMOS NVRAM concurrently, causing massive
headaches. Please don't turn this option on unless you are willing
to deal with extreme frustration.
Trying to write to a chip using --fmap will fail if the chip does
not yet have a valid fmap table (for example, a blank chip). Let's
omit this flag when writing the entire image.
This commit drops the verbatim `.config` files for coreboot that
were previously in the repository and converts them to NixOS-style
module configurations.
The big benefit of doing this is that the perl script in nixpkgs
that handles this will check to make sure that coreboot's Kconfig
machinery isn't silently ignoring any of our settings. It also
makes this configuration easier for end-users to customize.
This commit cleans up the selection of the serial console device and
gives it sensible default values (usually, the DB9 header on the
back I/O panel) on each platform.
This commit adds several useful scripts (alongside the coreboot
image) in a `main` expression, which should be the primary build
expression going forward.
The following scripts should exists on all platforms:
- flashrom wrappers:
- `flashrom.sh`
- `flash-write-all.sh`
- `flash-write-fallback.sh`
- `flash-write-normal.sh`
- scripts to select which image (normal or fallback) is used for the
next boot:
- `nextboot-show.sh`
- `nextboot-use-fallback.sh`
- `nextboot-use-normal.sh`
- a script to write an image to the em100 flash-chip-emulator device:
- `em100-write.sh`
This commit generalizes the selection and activation of the serial
console by promoting it to a top-level package-set member.
The top-level package set is starting to attract clutter, so I will
soon be moving all the non-package constitutents into a `config`
attrset.
This commit makes `hostPlatform` part of the packageset for more
consistent handling. A top-level `hostPlatform` argument is exposed
to the caller, in case they want to customize the `hostPlatform`
(compiler flags, etc).
The `hostPlatform` argument is inherited into the ownerboot package
set, where it will be overridden by `src/platform/*.nix` if it has
not been set explicitly.
Making `hostPlatform` part of the package set allows for more
sophisticated overriding schemes, for example adding additional
compiler flags or sanity-checking the flags that the user has
provided.
Since we (unfortunately) need to use different forks of flashrom for
different platforms, flashrom must be overrideable. Moving it into
the ownerboot packageset is the way to do that.
On amd64 platforms, booting ownerboot with the recovery jumper
installed will wipe the battery-backed nvram (aka "cmos" aka "rtc
nvram") and overwrite it with known-safe values taken from the
coreboot source code (`src/mainboard/asus/kgpe-d16/cmos.default`).
You should always do this when flashing a motherboard with ownerboot
for the first time.
This commit allows the user to customize the set of known-safe
values which are written when the recovery jumper is installed. To
do so, copy `src/mainboard/asus/kgpe-d16/cmos.default` out of
coreboot, edit to suit your tastes, and then override
`cmos-defaults` with the path to your customized `cmos.default`
file.
The microcode blob is only needed for Opteron 63xx chips. I have a
few of these, so I add the blob in a local overlay.
If other people are interested in this I will publish the overlay.
The 63xx chips are kind of rare and more expensive than the 62xx
chips -- their only real benefit is lower power draw. I ended up
receiving some by accident due to an incorrect eBay listing.
Adam Joseph