You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
From 931a025c1032bb00b084210c6b5ad0a4235ebfdb Mon Sep 17 00:00:00 2001
|
|
From: Your Name <you@example.com>
|
|
Date: Thu, 13 Apr 2023 00:07:56 -0700
|
|
Subject: [PATCH] amd/sb700/early_setup.c: select console properly
|
|
|
|
Currently, sb700/early_setup.c has this comment:
|
|
|
|
// XXX Serial port decode on LPC is hardcoded to 0x3f8
|
|
|
|
... and it unconditionally sets the output enable for ttyS0, even if
|
|
ttyS1 is also enabled. As a result, if coreboot is configured to
|
|
use ttyS1 for serial output, the romstage console output will appear
|
|
on *both* consoles.
|
|
|
|
This commit fixes that.
|
|
---
|
|
src/southbridge/amd/sb700/early_setup.c | 3 ++-
|
|
1 file changed, 2 insertions(+), 1 deletion(-)
|
|
|
|
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
|
|
index 70cf340c8e..4dfe6dd2ee 100644
|
|
--- a/src/southbridge/amd/sb700/early_setup.c
|
|
+++ b/src/southbridge/amd/sb700/early_setup.c
|
|
@@ -160,9 +160,10 @@ void sb7xx_51xx_lpc_init(void)
|
|
|
|
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
|
|
/* Decode port 0x3f8-0x3ff (Serial 0) */
|
|
- // XXX Serial port decode on LPC is hardcoded to 0x3f8
|
|
reg8 = pci_read_config8(dev, 0x44);
|
|
+#if CONFIG_TTYS0_BASE == 0x3f8
|
|
reg8 |= 1 << 6;
|
|
+#endif
|
|
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
|
|
#if CONFIG_TTYS0_BASE == 0x2f8
|
|
reg8 |= 1 << 7;
|
|
--
|
|
2.39.1
|
|
|