coreboot: add linux-command-line parameter for CONFIG_LINUX_COMMAND_LINE

src/coreboot/default.nix

@@ -6,6 +6,7 @@
 , initramfs_image    # path to the initramfs `cpio` archive
 , iasl               ? null # a specific iasl to use, if needed
 , console_loglevel   ? "7"
+, linux-command-line ? ""
 }:
 let
   version = "4.9";
@@ -82,6 +83,8 @@ stdenv.mkDerivation {
     sed -i 's/^CONFIG_DEFAULT_CONSOLE_LOGLEVEL//' .config
     echo 'CONFIG_DEFAULT_CONSOLE_LOGLEVEL_${console_loglevel}=y' >> .config
     echo 'CONFIG_DEFAULT_CONSOLE_LOGLEVEL=${console_loglevel}' >> .config
+    sed -i 's/^CONFIG_LINUX_COMMAND_LINE//' .config
+    echo 'CONFIG_LINUX_COMMAND_LINE="${linux-command-line}"' >> .config
     sed -i 's/^CONFIG_FMDFILE=.*//' .config
     echo 'CONFIG_FMDFILE="${fmap}"' >> .config
     sed -i 's/^CONFIG_PAYLOAD_FILE=.*//' .config

src/platform/am1i/coreboot.config

@@ -92,7 +92,6 @@ CONFIG_CBFS_SIZE=8387272
 # this is the internal header, which exists on both board variants
 CONFIG_UART_FOR_CONSOLE=0
 CONFIG_TTYS0_BASE=0x3f8
-CONFIG_LINUX_COMMAND_LINE="console=ttyS0,115200n8"
 
 # this is the back-panel connector, which exists only on the "more back-panel stuff" board variant
 #CONFIG_UART_FOR_CONSOLE=1

src/platform/am1i/default.nix

@@ -21,6 +21,7 @@
       coreboot-toolchain = with final.coreboot-toolchain; [ x64 i386 ];
       fmap = ./custom.fmap;
       config = ./coreboot.config;
+      linux-command-line="console=ttyS0,115200n8";
     }).overrideAttrs (a: {
       /*
       postConfigure = (a.postConfigure or "") + ''

src/platform/kevin/chromebook-flashrom-kludges.patch

@@ -0,0 +1,95 @@
+diff --git a/Makefile b/Makefile
+index 5c063e4..f657d2a 100644
+--- a/Makefile
++++ b/Makefile
+@@ -45,7 +45,7 @@ BUILD_DETAILS_FILE ?= build_details.txt
+ WARNERROR ?= yes
+ 
+ ifeq ($(WARNERROR), yes)
+-CFLAGS += -Werror
++#CFLAGS += -Werror
+ endif
+ 
+ ifdef LIBS_BASE
+@@ -579,7 +579,7 @@ PROGRAMMER_OBJS += cros_ec_lpc.o it87spi.o it85spi.o mec1308.o sb600spi.o wbsio_
+ PROGRAMMER_OBJS += ichspi.o ich_descriptors.o amd_imc.o
+ else
+ ifeq ($(ARCH),arm)
+-PROGRAMMER_OBJS += cros_ec_i2c.o
++#PROGRAMMER_OBJS += cros_ec_i2c.o
+ endif
+ NEED_LIBPCI += CONFIG_INTERNAL
+ endif
+diff --git a/cros_ec.c b/cros_ec.c
+index 4065d24..c25a207 100644
+--- a/cros_ec.c
++++ b/cros_ec.c
+@@ -428,14 +428,16 @@ int cros_ec_prepare(uint8_t *image, int size) {
+ 		return 1;
+ 	} else if (wp_status == 1) {
+ 		msg_pdbg("Attempting to disable EC soft WP.\n");
++/*
+ 		if (!set_wp(0)) {
+ 			msg_pdbg("EC soft WP disabled successfully.\n");
+ 			if (register_shutdown(cros_ec_restore_wp, NULL))
+ 				return 1;
+ 		} else {
++*/
+ 			msg_pdbg("Failed. Hardware WP might in effect or EC "
+ 				"needs to be rebooted first.\n");
+-		}
++//		}
+ 	} else {
+ 		msg_pdbg("EC soft WP is already disabled.\n");
+ 	}
+diff --git a/flashrom.c b/flashrom.c
+index 1b26dda..8c0e560 100644
+--- a/flashrom.c
++++ b/flashrom.c
+@@ -1074,16 +1074,19 @@ int probe_flash(int startchip, struct flashctx *fill_flash, int force)
+ 	 * needs to use (hwseq or swseq),
+ 	 * set the flashchips list here.
+ 	 */
++/*
+ 	switch (ich_generation) {
+ 	case CHIPSET_100_SERIES_SUNRISE_POINT:
+ 	case CHIPSET_APL:
+ 		flash_list = flashchips_hwseq;
+ 		break;
+ 	default:
++*/
+ 		flash_list = flashchips;
++/*
+ 		break;
+ 	}
+-
++*/
+ 	for (flash = flash_list + startchip; flash && flash->name; flash++) {
+ 		if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)
+ 			continue;
+diff --git a/internal.c b/internal.c
+index 441c9a2..9626c34 100644
+--- a/internal.c
++++ b/internal.c
+@@ -347,7 +347,7 @@ int internal_init(void)
+ 		 * Give preference to the cros_ec dev interface if it exists
+ 		 * and passes the "hello" test, otherwise fall back on raw I2C.
+ 		 */
+-		if (!cros_ec_probe_dev() || !cros_ec_probe_i2c(NULL))
++		if (!cros_ec_probe_dev() /*|| !cros_ec_probe_i2c(NULL)*/)
+ 			return 0;
+ 	}
+ #endif
+diff --git a/programmer.h b/programmer.h
+index 662ff33..f072138 100644
+--- a/programmer.h
++++ b/programmer.h
+@@ -604,7 +604,7 @@ enum ich_chipset {
+ };
+ 
+ #if CONFIG_INTERNAL == 1
+-enum ich_chipset ich_generation;
++//extern enum ich_chipset ich_generation;
+ extern uint32_t ichspi_bbar;
+ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
+ 		 enum ich_chipset ich_generation);

src/platform/kevin/coreboot.config

@@ -688,7 +688,6 @@ CONFIG_PAYLOAD_FIT=y
 # CONFIG_PAYLOAD_TIANOCORE is not set
 CONFIG_PAYLOAD_FILE="../linux/arch/arm64/boot/Image.fit"
 CONFIG_PAYLOAD_OPTIONS=""
-CONFIG_LINUX_COMMAND_LINE="console=ttyS2,115200n8"
 CONFIG_UNCOMPRESSED_PAYLOAD=y
 # CONFIG_COMPRESSED_PAYLOAD_LZMA is not set
 # CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set

src/platform/kevin/default.nix

@@ -72,6 +72,7 @@ in {
         fmap = ./custom.fmap;
         config = ./coreboot.config;
         coreboot-toolchain = with final.coreboot-toolchain; [ aarch64 ];
+        linux-command-line="console=ttyS2,115200n8";
       }).overrideAttrs (a: {
         postConfigure = ''
           echo CONFIG_ARM64_BL31_EXTERNAL_FILE=\"${atf}/bl31.elf\" >> .config

src/platform/kgpe/coreboot.config

@@ -637,7 +637,6 @@ CONFIG_PAYLOAD_LINUX=y
 CONFIG_PAYLOAD_FILE="../linux/arch/x86/boot/bzImage"
 CONFIG_PAYLOAD_OPTIONS=""
 # CONFIG_PXE is not set
-CONFIG_LINUX_COMMAND_LINE="console=ttyS1,115200n8"
 CONFIG_LINUX_INITRD=""
 # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
 # CONFIG_PAYLOAD_FIT_SUPPORT is not set

src/platform/kgpe/default.nix

@@ -42,6 +42,7 @@ in
       fmap = ./custom.fmap;
       config = ./coreboot.config;
       coreboot-toolchain = with final.coreboot-toolchain; [ x64 i386 ];
+      linux-command-line = "console=ttyS1,115200n8";
     }).overrideAttrs (a: {
       postConfigure = if update_microcode then ''
         echo CONFIG_CPU_MICROCODE_MULTIPLE_FILES=y >> .config