coreboot: several more kgpe patches
This commit integrates five more kgpe-d16 patches from my local
tree:
treewide: reduce many messages to BIOS_SPEW
southbridge/amd/sb700/lpc.c: leave LPC timeout mechanism enabled
I've been experiencing boot hangs during PNP enumeration of the LPC
bus. The southbridge chip comes with a mechanism to prevent
unresponsive/syncflooding LPC devices from wedging the system; let's
use it.
mainboard/asus/kgpe-d16/romstage.c: support console on ttyS1
Currently the romstage serial console initialization always
initializes SP1 (the DB9 header on the back of the motherboard).
Changing UART_FOR_CONSOLE simply causes the romstage to map the same
serial port at a different address (0x2f8).
This commit accounts for UART_FOR_CONSOLE (and its effect on
TTYS0_BASE) correctly: if UART_FOR_CONSOLE is changed from 0 to 1,
the romstage console output will be printed on the SP2 header (the
IDC ribbon header on the motherboard).
southbridge/amd/sb700/lpc.c: set SPI flash aperture to 16MB
The SPI flash aperture for the southbridge chip is set to 8MB, even
when a 16MB chip is used. Let's make the aperture large enough for
the maximum size chip that this board can accomodate.
amd/sb700/early_setup.c: select console properly
Currently, sb700/early_setup.c has this comment:
// XXX Serial port decode on LPC is hardcoded to 0x3f8
... and it unconditionally sets the output enable for ttyS0, even if
ttyS1 is also enabled. As a result, if coreboot is configured to
use ttyS1 for serial output, the romstage console output will appear
on *both* consoles.
This commit fixes that.
kgpe-d16: disable TPM
I have never heard of anybody using a TPM on this board, and the
fewer things we need to deal with during the somewhat-flaky LPC
init, the better.
master
Adam Joseph
2 years ago
parent
d41e364d2d
commit
8ee3c8a13b
@ -0,0 +1,38 @@
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From f960a8ecf4e84d6f759b38cd15890c1ab1900573 Mon Sep 17 00:00:00 2001
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From: Your Name <you@example.com>
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Date: Thu, 13 Apr 2023 00:30:35 -0700
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Subject: [PATCH 1/3] mainboard/asus/kgpe-d16/romstage.c: support console on
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ttyS1
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Currently the romstage serial console initialization always
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initializes SP1 (the DB9 header on the back of the motherboard).
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Changing UART_FOR_CONSOLE simply causes the romstage to map the same
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serial port at a different address (0x2f8).
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This commit accounts for UART_FOR_CONSOLE (and its effect on
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TTYS0_BASE) correctly: if UART_FOR_CONSOLE is changed from 0 to 1,
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the romstage console output will be printed on the SP2 header (the
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IDC ribbon header on the motherboard).
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---
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src/mainboard/asus/kgpe-d16/romstage.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
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index 9d84fe059a..e5599607d7 100644
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--- a/src/mainboard/asus/kgpe-d16/romstage.c
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+++ b/src/mainboard/asus/kgpe-d16/romstage.c
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@@ -514,7 +514,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
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/* Initialize early serial */
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+#if CONFIG_TTYS0_BASE == 0x3f8
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winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
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+#elif CONFIG_TTYS0_BASE == 0x2f8
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+ winbond_enable_serial(SERIAL_1_DEV, CONFIG_TTYS0_BASE);
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+#endif
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console_init();
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/* Disable LPC legacy DMA support to prevent lockup */
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--
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2.39.1
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@ -0,0 +1,33 @@
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From 212e744d043c4d448d10931631699a71bf69f472 Mon Sep 17 00:00:00 2001
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From: Your Name <you@example.com>
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Date: Thu, 13 Apr 2023 00:34:25 -0700
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Subject: [PATCH 2/3] southbridge/amd/sb700/lpc.c: leave LPC timeout mechanism
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enabled
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I've been experiencing boot hangs during PNP enumeration of the LPC
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bus. The southbridge chip comes with a mechanism to prevent
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unresponsive/syncflooding LPC devices from wedging the system; let's
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use it.
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---
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src/southbridge/amd/sb700/lpc.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
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index 47d588012a..1fbd498732 100644
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--- a/src/southbridge/amd/sb700/lpc.c
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+++ b/src/southbridge/amd/sb700/lpc.c
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@@ -59,9 +59,9 @@ static void lpc_init(struct device *dev)
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pci_write_config8(dev, 0x40, byte);
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}
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- /* Disable the timeout mechanism on LPC */
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+ /* Enable the timeout mechanism on LPC ("Sync Timeout Counter Enable") */
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byte = pci_read_config8(dev, 0x48);
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- byte &= ~(1 << 7);
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+ byte |= (1 << 7);
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pci_write_config8(dev, 0x48, byte);
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/* Disable LPC MSI Capability */
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--
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2.39.1
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@ -0,0 +1,151 @@
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From 7899c0aea9891384df5353eedbe1a23c4c4f428d Mon Sep 17 00:00:00 2001
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From: Your Name <you@example.com>
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Date: Thu, 13 Apr 2023 00:35:26 -0700
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Subject: [PATCH 3/3] treewide: reduce many messages to BIOS_SPEW
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---
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src/commonlib/cbfs.c | 6 ++++--
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src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++--
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src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 20 ++++++++++----------
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3 files changed, 16 insertions(+), 14 deletions(-)
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diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c
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index aa83ff759d..01cbde5dc8 100644
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--- a/src/commonlib/cbfs.c
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+++ b/src/commonlib/cbfs.c
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@@ -174,7 +174,9 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
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{
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struct cbfsf *prev;
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+#if 0
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LOG("Locating '%s'\n", name);
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+#endif
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prev = NULL;
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@@ -225,11 +227,11 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
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if (*type == 0)
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*type = ftype;
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}
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-
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+#if 0
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LOG("Found @ offset %zx size %zx\n",
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rdev_relative_offset(cbfs, &fh->metadata),
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region_device_sz(&fh->data));
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-
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+#endif
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/* Success. */
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return 0;
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}
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diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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index 34d1c1f73a..1d843b75dc 100644
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--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@@ -4016,12 +4016,12 @@ void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
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do {
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dword = Get_NB32(dev, 0x110);
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- printk(BIOS_DEBUG, ".");
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+ printk(BIOS_SPEW, ".");
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} while (dword & (1 << MemClrBusy));
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printk(BIOS_DEBUG, "\n");
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do {
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- printk(BIOS_DEBUG, ".");
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+ printk(BIOS_SPEW, ".");
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dword = Get_NB32(dev, 0x110);
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} while (!(dword & (1 << Dr_MemClrStatus)));
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printk(BIOS_DEBUG, "\n");
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diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
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index 3ca1a98abb..3bbf93bac3 100644
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--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
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+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
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@@ -282,7 +282,7 @@ uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, ui
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}
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}
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- printk(BIOS_INFO, "DIMM %d RttWr: %01x\n", dimm, term);
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+ printk(BIOS_SPEW, "DIMM %d RttWr: %01x\n", dimm, term);
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return term;
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}
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@@ -680,7 +680,7 @@ uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, u
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}
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}
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- printk(BIOS_INFO, "DIMM %d RttNom: %01x\n", dimm, term);
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+ printk(BIOS_SPEW, "DIMM %d RttNom: %01x\n", dimm, term);
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return term;
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}
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@@ -689,13 +689,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct)
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u32 dev = pDCTstat->dev_dct;
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u32 val;
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- printk(BIOS_DEBUG, "%s: Start\n", __func__);
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+ printk(BIOS_SPEW, "%s: Start\n", __func__);
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do {
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val = Get_NB32_DCT(dev, dct, 0x98);
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} while (!(val & (1 << DctAccessDone)));
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- printk(BIOS_DEBUG, "%s: Done\n", __func__);
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+ printk(BIOS_SPEW, "%s: Done\n", __func__);
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}
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static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct)
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@@ -740,7 +740,7 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
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u32 dev = pDCTstat->dev_dct;
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u32 val;
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- printk(BIOS_DEBUG, "%s: Start\n", __func__);
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+ printk(BIOS_SPEW, "%s: Start\n", __func__);
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val = Get_NB32_DCT(dev, dct, 0x7c);
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val &= ~0x00ffffff;
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@@ -752,7 +752,7 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
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val = Get_NB32_DCT(dev, dct, 0x7c);
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} while (val & (1 << SendMrsCmd));
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- printk(BIOS_DEBUG, "%s: Done\n", __func__);
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+ printk(BIOS_SPEW, "%s: Done\n", __func__);
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}
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u32 mct_MR2(struct MCTStatStruc *pMCTstat,
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@@ -1079,7 +1079,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
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u32 dev = pDCTstat->dev_dct;
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u32 dword;
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- printk(BIOS_DEBUG, "%s: Start\n", __func__);
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+ printk(BIOS_SPEW, "%s: Start\n", __func__);
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/*1.Program MrsAddress[10]=1
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2.Set SendZQCmd = 1
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@@ -1098,7 +1098,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
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/* 4.Wait 512 MEMCLKs */
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mct_Wait(300);
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- printk(BIOS_DEBUG, "%s: Done\n", __func__);
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+ printk(BIOS_SPEW, "%s: Done\n", __func__);
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}
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void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
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@@ -1108,7 +1108,7 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
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u32 dword;
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u32 dev = pDCTstat->dev_dct;
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- printk(BIOS_DEBUG, "%s: Start\n", __func__);
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+ printk(BIOS_SPEW, "%s: Start\n", __func__);
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|
if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
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/* 3.Program F2x[1,0]7C[EnDramInit]=1 */
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@@ -1206,5 +1206,5 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
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mct_DCTAccessDone(pDCTstat, dct);
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}
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- printk(BIOS_DEBUG, "%s: Done\n", __func__);
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+ printk(BIOS_SPEW, "%s: Done\n", __func__);
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}
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--
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|
2.39.1
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@ -0,0 +1,42 @@
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|
From 329f789c8cb0a1a6d4ce5cc5a2d7fa5ff9c6d95b Mon Sep 17 00:00:00 2001
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|
From: Your Name <you@example.com>
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|
Date: Wed, 12 Apr 2023 23:36:31 -0700
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|
Subject: [PATCH] kgpe-d16: disable TPM
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|
I have never heard of anybody using a TPM on this board, and the
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fewer things we need to deal with during the somewhat-flaky LPC
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|
init, the better.
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|
---
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|
src/mainboard/asus/kgpe-d16/Kconfig | 1 -
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|
src/mainboard/asus/kgpe-d16/devicetree.cb | 3 ---
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|
2 files changed, 4 deletions(-)
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|
diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
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|
index d87d9269cc..c6b2de3ab9 100644
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|
--- a/src/mainboard/asus/kgpe-d16/Kconfig
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|
+++ b/src/mainboard/asus/kgpe-d16/Kconfig
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|
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS
|
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|
select BOARD_ROMSIZE_KB_2048
|
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|
select ENABLE_APIC_EXT_ID
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|
select SPI_FLASH
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|
- select MAINBOARD_HAS_LPC_TPM
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|
select HAVE_ACPI_RESUME
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|
select DRIVERS_I2C_W83795
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|
select DRIVERS_ASPEED_AST2050
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|
diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
|
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|
index 9039f6dea2..ff2023ddd0 100644
|
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|
--- a/src/mainboard/asus/kgpe-d16/devicetree.cb
|
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|
+++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
|
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|
@@ -214,9 +214,6 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
|
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|
device pnp 2e.d off end # VID_BUSSEL
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|
device pnp 2e.f off end # GPIO_PP_OD
|
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|
end
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|
- chip drivers/pc80/tpm
|
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|
- device pnp 4e.0 on end # TPM module
|
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|
- end
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|
end
|
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|
device pci 14.4 on # Bridge
|
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|
device pci 1.0 on end # VGA
|
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|
--
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|
2.39.1
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|
|
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@ -0,0 +1,38 @@
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|
From 931a025c1032bb00b084210c6b5ad0a4235ebfdb Mon Sep 17 00:00:00 2001
|
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|
From: Your Name <you@example.com>
|
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|
Date: Thu, 13 Apr 2023 00:07:56 -0700
|
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|
Subject: [PATCH] amd/sb700/early_setup.c: select console properly
|
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|
|
||||||
|
Currently, sb700/early_setup.c has this comment:
|
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|
|
||||||
|
// XXX Serial port decode on LPC is hardcoded to 0x3f8
|
||||||
|
|
||||||
|
... and it unconditionally sets the output enable for ttyS0, even if
|
||||||
|
ttyS1 is also enabled. As a result, if coreboot is configured to
|
||||||
|
use ttyS1 for serial output, the romstage console output will appear
|
||||||
|
on *both* consoles.
|
||||||
|
|
||||||
|
This commit fixes that.
|
||||||
|
---
|
||||||
|
src/southbridge/amd/sb700/early_setup.c | 3 ++-
|
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|
1 file changed, 2 insertions(+), 1 deletion(-)
|
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|
|
||||||
|
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
|
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|
index 70cf340c8e..4dfe6dd2ee 100644
|
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|
--- a/src/southbridge/amd/sb700/early_setup.c
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|
+++ b/src/southbridge/amd/sb700/early_setup.c
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|
@@ -160,9 +160,10 @@ void sb7xx_51xx_lpc_init(void)
|
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|
|
||||||
|
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
|
||||||
|
/* Decode port 0x3f8-0x3ff (Serial 0) */
|
||||||
|
- // XXX Serial port decode on LPC is hardcoded to 0x3f8
|
||||||
|
reg8 = pci_read_config8(dev, 0x44);
|
||||||
|
+#if CONFIG_TTYS0_BASE == 0x3f8
|
||||||
|
reg8 |= 1 << 6;
|
||||||
|
+#endif
|
||||||
|
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)
|
||||||
|
#if CONFIG_TTYS0_BASE == 0x2f8
|
||||||
|
reg8 |= 1 << 7;
|
||||||
|
--
|
||||||
|
2.39.1
|
||||||
|
|
||||||
@ -0,0 +1,30 @@
|
|||||||
|
From d3154d80bd53c5de3395ae0a50beccbc11af4a9d Mon Sep 17 00:00:00 2001
|
||||||
|
From: Your Name <you@example.com>
|
||||||
|
Date: Thu, 13 Apr 2023 00:19:19 -0700
|
||||||
|
Subject: [PATCH] southbridge/amd/sb700/lpc.c: set SPI flash aperture to 16MB
|
||||||
|
|
||||||
|
The SPI flash aperture for the southbridge chip is set to 8MB, even
|
||||||
|
when a 16MB chip is used. Let's make the aperture large enough for
|
||||||
|
the maximum size chip that this board can accomodate.
|
||||||
|
---
|
||||||
|
src/southbridge/amd/sb700/lpc.c | 4 ++--
|
||||||
|
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
|
||||||
|
index 857503a7ed..47d588012a 100644
|
||||||
|
--- a/src/southbridge/amd/sb700/lpc.c
|
||||||
|
+++ b/src/southbridge/amd/sb700/lpc.c
|
||||||
|
@@ -98,8 +98,8 @@ static void sb700_lpc_read_resources(struct device *dev)
|
||||||
|
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||||
|
|
||||||
|
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||||
|
- res->base = 0xff800000;
|
||||||
|
- res->size = 0x00800000; /* 8 MB for flash */
|
||||||
|
+ res->base = 0xff000000;
|
||||||
|
+ res->size = 0x01000000; /* 16 MB for flash */
|
||||||
|
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
||||||
|
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||||
|
|
||||||
|
--
|
||||||
|
2.39.1
|
||||||
|
|
||||||
Loading…
Reference in New Issue