eliminate "magic numbers", support 8mbyte single-image flash chips

Prior to this commit, ownerboot had quite a lot of "magic addresses"
and flash chip layouts.  This commit eliminates all of them.

All flash chip geometry is now computed from first principles and
two parameters:

  1. The flash chip size
  2. The number of images per chip (two means NORMAL/FALLBACK)

If (flash-chip-size / num-images) is too small, coreboot's build
process will notice this and fail.

It should be possible to build a single-image (i.e. no FALLBACK)
ownerboot for use on 8mbyte flash chips, which lets people try this
out without having to buy a new flash chip or (in the case of the
rk3399-gru-kevin laptop) doing any soldering.
master
Adam Joseph 1 year ago
parent c72e1a55be
commit 9dd5bdf298

@ -29,6 +29,8 @@ nix-build --option trusted-public-keys "" src -A am1i.image # am1-i AMD kabin
nix-build --option trusted-public-keys "" src -A kevin.image # Samsung chromebook rk3399 arm64 nix-build --option trusted-public-keys "" src -A kevin.image # Samsung chromebook rk3399 arm64
``` ```
By default ownerboot builds for 16mbyte flash chips with two (NORMAL/FALLBACK) images per chip. You can produce a 8mbyte single-image-per-chip by appending `--arg flash-chip-size-in-mbytes 8` to any of the above commands.
Details: [doc/build.md](doc/build.md). Details: [doc/build.md](doc/build.md).
## All that compiling and it just dumps me at a bash prompt? ## All that compiling and it just dumps me at a bash prompt?

@ -6,6 +6,8 @@
, config ? throw "you must provide a <nixpkgs/lib/modules.nix>-style structuredConfig" , config ? throw "you must provide a <nixpkgs/lib/modules.nix>-style structuredConfig"
, iasl ? null # a specific iasl to use, if needed , iasl ? null # a specific iasl to use, if needed
, console_loglevel ? "6" # 8=SPEW, 7=DEBUG, 6=INFO , console_loglevel ? "6" # 8=SPEW, 7=DEBUG, 6=INFO
, flash-chip-size-in-mbytes
, images-per-flash-chip
# Can be null or an integer (0, 1, 2, ...); note: the mapping from # Can be null or an integer (0, 1, 2, ...); note: the mapping from
# these integers to ttyS* values is occasionally not the identity # these integers to ttyS* values is occasionally not the identity
@ -25,6 +27,8 @@ let
hash = "sha256-lX6QnUS4a/F4Y68qK9i45O4OP+UEjHlCK+YaKJOQLUo="; hash = "sha256-lX6QnUS4a/F4Y68qK9i45O4OP+UEjHlCK+YaKJOQLUo=";
fetchSubmodules = false; fetchSubmodules = false;
}; };
flash-chip-size-in-kbytes = flash-chip-size-in-mbytes * 1024;
flash-chip-size-in-bytes = flash-chip-size-in-kbytes * 1024;
in in
stdenv.mkDerivation { stdenv.mkDerivation {
pname = "coreboot"; pname = "coreboot";
@ -114,7 +118,9 @@ stdenv.mkDerivation {
./patches/0021-am1i-omit-amdfw.rom-completely-it-has-broken-address.patch ./patches/0021-am1i-omit-amdfw.rom-completely-it-has-broken-address.patch
# normal/fallback functionality (ownerboot-specific) # normal/fallback functionality (ownerboot-specific)
./patches/0017-use_fallback-platform-independent-part.patch (if images-per-flash-chip <= 1
then ./patches/0017-rename_coreboot_to_fallback.patch
else ./patches/0017-use_fallback-platform-independent-part.patch)
./patches/0018-use_fallback-rk3399-gru-kevin-use-fallback-if-watchd.patch ./patches/0018-use_fallback-rk3399-gru-kevin-use-fallback-if-watchd.patch
./patches/0019-use_fallback-rk3399-gru-kevin-update-for-coreboot-4..patch ./patches/0019-use_fallback-rk3399-gru-kevin-update-for-coreboot-4..patch
./patches/0020-use_fallback-kgpe-d16-implement-using-nvram-with-cmo.patch ./patches/0020-use_fallback-kgpe-d16-implement-using-nvram-with-cmo.patch
@ -152,6 +158,11 @@ stdenv.mkDerivation {
DEFAULT_CONSOLE_LOGLEVEL = lib.mkForce (freeform (toString console_loglevel)); DEFAULT_CONSOLE_LOGLEVEL = lib.mkForce (freeform (toString console_loglevel));
FMDFILE = lib.mkForce (freeform "${fmap}"); FMDFILE = lib.mkForce (freeform "${fmap}");
PAYLOAD_NONE = lib.mkForce yes; PAYLOAD_NONE = lib.mkForce yes;
"COREBOOT_ROMSIZE_KB_${toString flash-chip-size-in-kbytes}" = lib.mkForce yes;
# TODO: the following two options might be unnecessary
ROM_SIZE = lib.mkForce (freeform "0x${lib.toHexString flash-chip-size-in-bytes}");
COREBOOT_ROMSIZE_KB = lib.mkForce (freeform (toString flash-chip-size-in-kbytes));
} // lib.optionalAttrs (uart-for-console != null) { } // lib.optionalAttrs (uart-for-console != null) {
UART_FOR_CONSOLE = lib.mkForce (freeform "${builtins.toString uart-for-console}"); UART_FOR_CONSOLE = lib.mkForce (freeform "${builtins.toString uart-for-console}");
} // lib.optionalAttrs (iasl != null) { } // lib.optionalAttrs (iasl != null) {

@ -0,0 +1,212 @@
From db4da17916cbeed002e4fa8422ed2cdd82b3b26f Mon Sep 17 00:00:00 2001
From: Your Name <you@example.com>
Date: Thu, 2 Dec 2021 23:39:00 -0800
Subject: [PATCH] use_fallback(): platform-independent part
This commit implements the platform-independent part of a two-image
fallback system.
The images are stored as separate FMAP regions, with each region
containing a complete CBFS structure. The names of the two FMAP
regions, NORMAL and FALLBACK, are hardcoded in
src/include/bootblock_common.h.
There is only one copy of the bootblock. Where it is kept is a
platform-specific matter.
The bootblock will call use_fallback(); if this function returns 0
then the NORMAL FMAP region is used for CBFS lookups. If it returns
1 then the FALLBACK FMAP region is used for CBFS lookups. The default
__weak implementation always returns 1.
Any CBFS accesses from romcc stages will always use the FALLBACK copy,
since the romcc version of the CBFS-walking routine does not
understand FMAP partitions. This means that the `cmos.layout` from
the FALLBACK region is used for the majority of the boot process.
---
Makefile.inc | 5 +++--
src/drivers/pc80/rtc/mc146818rtc.c | 9 +++++++--
src/include/bootblock_common.h | 4 ++++
src/lib/bootblock.c | 1 +
src/lib/cbfs.c | 9 +++++++--
src/lib/prog_loaders.c | 6 +++++-
util/cbfstool/cbfs_sections.h | 2 +-
util/scripts/dts-to-fmd.sh | 6 +++---
8 files changed, 31 insertions(+), 11 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 44c58be5b78..fde7511ee82 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -727,7 +727,7 @@ extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-)
#
# This is the default implementation. When using a boot strategy employing
# multiple CBFSes in fmap regions, override it.
-regions-for-file ?= COREBOOT
+regions-for-file ?= FALLBACK
ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y)
cbfs-autogen-attributes=-g
@@ -999,7 +999,7 @@ else # ifeq ($(CONFIG_ARCH_X86),y)
-b -4
rm -f $@.tmp.2
endif # ifeq ($(CONFIG_ARCH_X86),y)
- $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS)
+ $(CBFSTOOL) $@.tmp add-master-header -rFALLBACK $(TS_OPTIONS)
$(prebuild-files) true
mv $@.tmp $@
else # ifneq ($(CONFIG_UPDATE_IMAGE),y)
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index 3b22a46298b..ef1ef7a275b 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -250,9 +250,14 @@ static enum cb_err locate_cmos_layout(struct region_device *rdev)
* we have multiple CMOS layout files and to locate them we'd need to
* include VBOOT into SMM...
*
- * Support only one CMOS layout in the 'COREBOOT' region for now.
+ * Support only one CMOS layout in the 'NORMAL' region for now.
*/
- if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin",
+ if (cbfs_locate_file_in_region(&fh,
+ // always use FALLBACK because we can't yet access the
+ // nvram in order to figure out which mode (normal/fallback)
+ // we are in.
+ "FALLBACK",
+ "cmos_layout.bin",
&cbfs_type)) {
printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. "
"Options are disabled\n");
diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h
index 7af0cebe633..21a5efee901 100644
--- a/src/include/bootblock_common.h
+++ b/src/include/bootblock_common.h
@@ -21,6 +21,9 @@
#include <timestamp.h>
#include <types.h>
+#define FMAP_REGION_FALLBACK "FALLBACK"
+#define FMAP_REGION_NORMAL "FALLBACK"
+
/*
* These are defined as weak no-ops that can be overridden by mainboard/SoC.
* The 'early' variants are called prior to console initialization. Also, the
@@ -31,6 +34,7 @@ void bootblock_mainboard_early_init(void);
void bootblock_mainboard_init(void);
void bootblock_soc_early_init(void);
void bootblock_soc_init(void);
+int use_fallback(void);
/*
* C code entry point for the boot block.
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index f2ada522eb5..890c19f3160 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -28,6 +28,7 @@ __weak void bootblock_mainboard_early_init(void) { /* no-op */ }
__weak void bootblock_soc_early_init(void) { /* do nothing */ }
__weak void bootblock_soc_init(void) { /* do nothing */ }
__weak void bootblock_mainboard_init(void) { /* do nothing */ }
+__weak int use_fallback(void) { /* always */ return 1; }
asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp,
struct timestamp_entry *timestamps, size_t num_timestamps)
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index a5c9f852386..076ff1a8a97 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -26,6 +26,7 @@
#include <timestamp.h>
#include <fmap.h>
#include "fmap_config.h"
+#include "bootblock_common.h"
#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x)
#define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
@@ -273,7 +274,7 @@ out:
return 0;
}
-/* This only supports the "COREBOOT" fmap region. */
+/* This now supports both the "NORMAL" and "FALLBACK" fmap regions. */
static int cbfs_master_header_props(struct cbfs_props *props)
{
struct cbfs_header header;
@@ -286,7 +287,11 @@ static int cbfs_master_header_props(struct cbfs_props *props)
if (bdev == NULL)
return -1;
- size_t fmap_top = ___FMAP__COREBOOT_BASE + ___FMAP__COREBOOT_SIZE;
+ size_t fmap_top =
+ use_fallback()
+ ? (___FMAP__FALLBACK_BASE + ___FMAP__FALLBACK_SIZE)
+ : (___FMAP__FALLBACK_BASE + ___FMAP__FALLBACK_SIZE)
+ ;
/* Find location of header using signed 32-bit offset from
* end of CBFS region. */
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index a9c9addbc60..10b5746e384 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -30,6 +30,7 @@
#include <symbols.h>
#include <timestamp.h>
#include <fit_payload.h>
+#include <bootblock_common.h>
/* Only can represent up to 1 byte less than size_t. */
const struct mem_region_device addrspace_32bit =
@@ -41,7 +42,10 @@ int prog_locate(struct prog *prog)
cbfs_prepare_program_locate();
- if (cbfs_boot_locate(&file, prog_name(prog), NULL))
+ if (cbfs_locate_file_in_region(&file,
+ use_fallback() ? FMAP_REGION_FALLBACK : FMAP_REGION_NORMAL,
+ prog_name(prog),
+ NULL))
return -1;
cbfsf_file_type(&file, &prog->cbfs_type);
diff --git a/util/cbfstool/cbfs_sections.h b/util/cbfstool/cbfs_sections.h
index 3526f8d94c3..fe2011cbb34 100644
--- a/util/cbfstool/cbfs_sections.h
+++ b/util/cbfstool/cbfs_sections.h
@@ -21,7 +21,7 @@
#include <stdbool.h>
#define SECTION_NAME_FMAP "FMAP"
-#define SECTION_NAME_PRIMARY_CBFS "COREBOOT"
+#define SECTION_NAME_PRIMARY_CBFS "FALLBACK"
#define SECTION_ANNOTATION_CBFS "CBFS"
diff --git a/util/scripts/dts-to-fmd.sh b/util/scripts/dts-to-fmd.sh
index b468b35bcd7..6a022933022 100755
--- a/util/scripts/dts-to-fmd.sh
+++ b/util/scripts/dts-to-fmd.sh
@@ -91,9 +91,9 @@ for region in $FMAP_REGIONS; do
# special handling: rename BOOT_STUB to COREBOOT, mark them as CBFS
if [ "${REGION_NAME}" = "BOOT_STUB" ]; then
- REGION_NAME="COREBOOT"
+ REGION_NAME="NORMAL"
fi
- if [ "${REGION_NAME}" = "COREBOOT" ]; then
+ if [ "${REGION_NAME}" = "NORMAL" ]; then
IS_CBFS="(CBFS)"
fi
@@ -105,7 +105,7 @@ for region in $FMAP_REGIONS; do
# special handling: COREBOOT region at 0, inject a 128K bootblock
# The size may need changes to accommodate the chipsets,
# but should work for now.
- if [ "${REGION_NAME}" = "COREBOOT" -a \
+ if [ "${REGION_NAME}" = "NORMAL" -a \
$(( ${REGION_START} )) -eq 0 ]; then
printf "\n${PREFIX}BOOTBLOCK@0 128K"
LOCAL_REGION_START=$(( ${LOCAL_REGION_START} + 128*1024 ))
--
2.39.1

@ -3,11 +3,16 @@
, pkgsFun ? import nixpkgs , pkgsFun ? import nixpkgs
, hostPlatform ? null # if left `null` this will be set based on the ./platform/ , hostPlatform ? null # if left `null` this will be set based on the ./platform/
, six-initrd ? import ../upstream/six-initrd/default.nix , six-initrd ? import ../upstream/six-initrd/default.nix
, flash-chip-size-in-mbytes ? 16
, images-per-flash-chip ? if flash-chip-size-in-mbytes >= 16 then 2 else 1
}: }:
let let
nixpkgsArgs = { config.allowNonSource = false; }; nixpkgsArgs = { config.allowNonSource = false; };
nixpkgsOnBuildForBuild = pkgsFun nixpkgsArgs; nixpkgsOnBuildForBuild = pkgsFun nixpkgsArgs;
chip-name = {
"16" = "GD25Q128C";
"8" = "GD25Q64C";
}."${toString flash-chip-size-in-mbytes}";
ownerboot = { overlays }: let ownerboot = { overlays }: let
base = final: prev: { base = final: prev: {
AAAAAASomeThingsBuildTooMuch = throw '' AAAAAASomeThingsBuildTooMuch = throw ''
@ -28,6 +33,9 @@ let
# TODO(amjoseph): move this into a `config` attrset # TODO(amjoseph): move this into a `config` attrset
console-device = throw "platforms must override this (example: \"ttyS0\")"; console-device = throw "platforms must override this (example: \"ttyS0\")";
console-parameters = "115200n8"; console-parameters = "115200n8";
inherit flash-chip-size-in-mbytes images-per-flash-chip;
flash-chip-size-in-bytes = flash-chip-size-in-mbytes * 1024 * 1024;
image-size-in-bytes = final.flash-chip-size-in-mbytes / final.images-per-flash-chip;
linux-command-line = linux-command-line =
let console = "${final.console-device},${final.console-parameters}"; let console = "${final.console-device},${final.console-parameters}";
in "console=${console} earlyprintk=${console}"; in "console=${console} earlyprintk=${console}";
@ -60,7 +68,7 @@ let
# totally different platform than the Device Under Test. # totally different platform than the Device Under Test.
# TODO(amjoseph): don't hardwire the chip type here # TODO(amjoseph): don't hardwire the chip type here
'' ''
em100 -v --stop --holdpin float -c GD25Q128C --download ${final.image}/coreboot.rom --start --trace em100 -v --stop --holdpin float -c ${chip-name} --download ${final.image}/coreboot.rom --start --trace
''; '';
# #
# TODO(amjoseph): add a sanity check that (a) the image being # TODO(amjoseph): add a sanity check that (a) the image being

@ -9,6 +9,7 @@
, payload-name ? "payload" , payload-name ? "payload"
, initramfs ? null # initramfs `cpio` archive , initramfs ? null # initramfs `cpio` archive
, linux-command-line ? null , linux-command-line ? null
, images-per-flash-chip
}: }:
nixpkgsOnBuildForHost.stdenv.mkDerivation { nixpkgsOnBuildForHost.stdenv.mkDerivation {
@ -39,7 +40,7 @@ nixpkgsOnBuildForHost.stdenv.mkDerivation {
] ++ [ ] ++ [
"\n" "\n"
]); ]);
in '' in (''
runHook preBuild runHook preBuild
cp ${coreboot}/coreboot.rom . cp ${coreboot}/coreboot.rom .
chmod +w coreboot.rom chmod +w coreboot.rom
@ -47,15 +48,17 @@ nixpkgsOnBuildForHost.stdenv.mkDerivation {
${update-cbfs "FALLBACK"} ${update-cbfs "FALLBACK"}
cbfstool coreboot.rom print -rFALLBACK cbfstool coreboot.rom print -rFALLBACK
'' + lib.optionalString (images-per-flash-chip > 1) ''
# unfortunately this is the only way to trick cbfstool into # unfortunately this is the only way to trick cbfstool into
# putting a "header pointer" in both regions: # putting a "header pointer" in both regions:
cbfstool coreboot.rom read -r FALLBACK -f half.img cbfstool coreboot.rom read -r FALLBACK -f half.img
cbfstool coreboot.rom write -F -r NORMAL -f half.img cbfstool coreboot.rom write -F -r NORMAL -f half.img
rm half.img rm half.img
cbfstool coreboot.rom print -rNORMAL cbfstool coreboot.rom print -rNORMAL
'' + ''
runHook postBuild runHook postBuild
''; '');
installPhase = '' installPhase = ''
runHook preBuild runHook preBuild

@ -3,7 +3,16 @@
}: }:
{ {
overlays = common_amd64.overlays ++ [(final: prev: { overlays = common_amd64.overlays ++ [(final: prev:
let
fmap-size-in-bytes = 1024;
flash-chip-bytes-per-image = final.flash-chip-size-in-bytes / final.images-per-flash-chip;
cbfs-size-in-bytes = flash-chip-bytes-per-image - fmap-size-in-bytes;
fallback-image-address-in-bytes =
if final.images-per-flash-chip <= 1
then 0
else flash-chip-bytes-per-image;
in {
platform_name = "am1i"; platform_name = "am1i";
@ -19,7 +28,7 @@
console-device = "ttyS1"; console-device = "ttyS1";
payload = "${final.kernel}/bzImage"; payload = "${final.kernel}/bzImage";
fmap = final.nixpkgsOnBuildForBuild.writeText "custom.fmap" '' fmap = final.nixpkgsOnBuildForBuild.writeText "custom.fmap" (''
# #
# Note: on x86 platforms the SPI flash is mapped into or copied into # Note: on x86 platforms the SPI flash is mapped into or copied into
# the topmost X bytes of memory, and the very topmost word of memory # the topmost X bytes of memory, and the very topmost word of memory
@ -28,17 +37,21 @@
# controls the reset vector and any other chunk of the flash, the game # controls the reset vector and any other chunk of the flash, the game
# is over. # is over.
# #
FLASH@0 0x1000000 { FLASH@0 0x${lib.toHexString final.flash-chip-size-in-bytes} {
BIOS@0 0x1000000 { BIOS@0 0x${lib.toHexString final.flash-chip-size-in-bytes} {
'' + lib.optionalString (final.images-per-flash-chip > 1) ''
# read-write zone # read-write zone
NORMAL(CBFS) @ 0x400 0x7FFC00 NORMAL(CBFS) @ 0x${lib.toHexString fmap-size-in-bytes} 0x${lib.toHexString cbfs-size-in-bytes}
'' + ''
'' + lib.optionalString (final.images-per-flash-chip > 1) ''
# read-only zone (eventually) # read-only zone (eventually)
FMAP @ 0x800000 0x400 FMAP @ 0x${lib.toHexString flash-chip-bytes-per-image} 0x${lib.toHexString fmap-size-in-bytes}
FALLBACK(CBFS) @ 0x800400 0x7FFC00 FALLBACK(CBFS) @ 0x${lib.toHexString (flash-chip-bytes-per-image + fmap-size-in-bytes)} 0x${lib.toHexString cbfs-size-in-bytes}
'' + ''
} }
} }
''; '');
coreboot = (prev.coreboot.override { coreboot = (prev.coreboot.override {
iasl = final.iasl_20180531; iasl = final.iasl_20180531;
@ -49,7 +62,6 @@
VENDOR_ASUS = lib.mkForce yes; VENDOR_ASUS = lib.mkForce yes;
BOARD_ASUS_AM1I_A = lib.mkForce yes; BOARD_ASUS_AM1I_A = lib.mkForce yes;
CBFS_SIZE = lib.mkForce (freeform "0x7FFAC8");
CONSOLE_CBMEM = lib.mkForce no; CONSOLE_CBMEM = lib.mkForce no;
DRIVERS_INTEL_WIFI = lib.mkForce no; DRIVERS_INTEL_WIFI = lib.mkForce no;
HUDSON_XHCI_ENABLE = lib.mkForce no; HUDSON_XHCI_ENABLE = lib.mkForce no;

@ -36,7 +36,20 @@ let
in { in {
overlays = common_arm64.overlays ++ [(final: prev: { overlays = common_arm64.overlays ++ [(final: prev:
let
bootblock-size-in-kbytes = 128;
fmap-address-in-bytes = bootblock-size-in-kbytes * 1024;
fmap-size-in-bytes = 1024;
flash-chip-bytes-per-image = final.flash-chip-size-in-bytes / final.images-per-flash-chip;
cbfs-alignment-in-bytes = 4 * 1024; # CBFS should be at a 4k-aligned address
cbfs-address-in-bytes =
(builtins.ceil
((1.0 * (fmap-address-in-bytes + fmap-size-in-bytes))
/ cbfs-alignment-in-bytes))
* cbfs-alignment-in-bytes;
cbfs-size-in-bytes = flash-chip-bytes-per-image - cbfs-address-in-bytes;
in {
nixpkgsOnBuildForHost = prev.nixpkgsOnBuildForBuild.pkgsCross.aarch64-multiplatform; nixpkgsOnBuildForHost = prev.nixpkgsOnBuildForBuild.pkgsCross.aarch64-multiplatform;
platform_name = "kevin"; platform_name = "kevin";
@ -75,7 +88,7 @@ in {
}; };
payload = "${final.fit}/Image.fit"; payload = "${final.fit}/Image.fit";
fmap = final.nixpkgsOnBuildForBuild.writeText "custom.fmap" '' fmap = final.nixpkgsOnBuildForBuild.writeText "custom.fmap" (''
# layout for firmware when flash address space matches used address layout # layout for firmware when flash address space matches used address layout
# +-------------+ <-- 0 # +-------------+ <-- 0
# | unspecified | # | unspecified |
@ -87,18 +100,19 @@ in {
# | CBFS | # | CBFS |
# +-------------+ <-- ROM_SIZE # +-------------+ <-- ROM_SIZE
FLASH@0 0x1000000 { FLASH@0 0x${lib.toHexString (final.flash-chip-size-in-mbytes * 1024 * 1024)} {
# read-only zone (eventually) # read-only zone
BOOTBLOCK 128K BOOTBLOCK ${toString bootblock-size-in-kbytes}K
FMAP @ 0x20000 0x400 FMAP @ 0x${lib.toHexString fmap-address-in-bytes} 0x${lib.toHexString fmap-size-in-bytes}
# gap here from 0x20400 to keep FALLBACK 4k-aligned FALLBACK(CBFS) @ 0x${lib.toHexString cbfs-address-in-bytes} 0x${lib.toHexString cbfs-size-in-bytes}
FALLBACK(CBFS) @ 0x21000 0x7DF000
'' + lib.optionalString (final.images-per-flash-chip > 1) ''
# read-write zone # read-write zone
NORMAL(CBFS) @ 0x800000 0x7DF000 NORMAL(CBFS) @ 0x${lib.toHexString flash-chip-bytes-per-image} 0x${lib.toHexString cbfs-size-in-bytes}
MISC @ 0xFDF000 0x21000 # 132k MISC @ 0x${lib.toHexString (flash-chip-bytes-per-image + cbfs-size-in-bytes)} 0x${lib.toHexString (flash-chip-bytes-per-image - cbfs-size-in-bytes)}
'' + ''
} }
''; '');
image = prev.image.override { image = prev.image.override {
initramfs = null; # it is part of the FIT image initramfs = null; # it is part of the FIT image
@ -119,9 +133,7 @@ in {
# maybe enable this # maybe enable this
#RK3399_SPREAD_SPECTRUM_DDR = lib.mkForce yes; #RK3399_SPREAD_SPECTRUM_DDR = lib.mkForce yes;
CBFS_SIZE = lib.mkForce (freeform "0x6CECD8"); CBFS_SIZE = lib.mkForce (freeform "0x${lib.toHexString cbfs-size-in-bytes}");
ROM_SIZE = lib.mkForce (freeform "0x${lib.toHexString (16 * 1024 * 1024)}");
COREBOOT_ROMSIZE_KB_16384 = lib.mkForce yes;
CONSOLE_SERIAL = lib.mkForce yes; CONSOLE_SERIAL = lib.mkForce yes;
#BOOTBLOCK_CONSOLE = lib.mkForce yes; #BOOTBLOCK_CONSOLE = lib.mkForce yes;

@ -3,7 +3,16 @@
}: }:
{ {
overlays = common_amd64.overlays ++ [(final: prev: { overlays = common_amd64.overlays ++ [(final: prev:
let
fmap-size-in-bytes = 1024;
flash-chip-bytes-per-image = final.flash-chip-size-in-bytes / final.images-per-flash-chip;
cbfs-size-in-bytes = flash-chip-bytes-per-image - fmap-size-in-bytes;
fallback-image-address-in-bytes =
if final.images-per-flash-chip <= 1
then 0
else flash-chip-bytes-per-image;
in {
platform_name = "kgpe"; platform_name = "kgpe";
@ -43,7 +52,7 @@
cmos-default = null; cmos-default = null;
payload = "${final.kernel}/bzImage"; payload = "${final.kernel}/bzImage";
fmap = final.nixpkgsOnBuildForBuild.writeText "custom.fmap" '' fmap = final.nixpkgsOnBuildForBuild.writeText "custom.fmap" (''
# #
# Note: on x86 platforms the SPI flash is copied into the topmost X # Note: on x86 platforms the SPI flash is copied into the topmost X
# bytes of memory, and the very topmost word of memory is the "reset # bytes of memory, and the very topmost word of memory is the "reset
@ -51,17 +60,19 @@
# must protect the TOPMOST half of memory; if an attacker controls the # must protect the TOPMOST half of memory; if an attacker controls the
# reset vector and any other chunk of the flash, the game is over. # reset vector and any other chunk of the flash, the game is over.
# #
FLASH@0 0x1000000 { FLASH@0 0x${lib.toHexString final.flash-chip-size-in-bytes} {
BIOS@0 0x1000000 { BIOS@0 0x${lib.toHexString final.flash-chip-size-in-bytes} {
'' + lib.optionalString (final.images-per-flash-chip > 1) ''
# read-write zone # read-write zone
NORMAL(CBFS) @ 0x400 0x7FFC00 NORMAL(CBFS) @ 0x${lib.toHexString fmap-size-in-bytes} 0x${lib.toHexString cbfs-size-in-bytes}
'' + ''
# read-only zone (eventually) # read-only zone
FMAP @ 0x800000 0x400 FMAP @ 0x${lib.toHexString fallback-image-address-in-bytes} 0x${lib.toHexString fmap-size-in-bytes}
FALLBACK(CBFS) @ 0x800400 0x7FFC00 FALLBACK(CBFS) @ 0x${lib.toHexString (fallback-image-address-in-bytes + fmap-size-in-bytes)} 0x${lib.toHexString cbfs-size-in-bytes}
} }
} }
''; '');
coreboot = (prev.coreboot.override { coreboot = (prev.coreboot.override {
iasl = final.iasl_20180531; iasl = final.iasl_20180531;
@ -97,8 +108,7 @@
MAINBOARD_SMBIOS_PRODUCT_NAME = lib.mkForce (freeform "KGPE-D16"); MAINBOARD_SMBIOS_PRODUCT_NAME = lib.mkForce (freeform "KGPE-D16");
MAINBOARD_SMBIOS_MANUFACTURER = lib.mkForce (freeform "ASUS"); MAINBOARD_SMBIOS_MANUFACTURER = lib.mkForce (freeform "ASUS");
CBFS_SIZE = lib.mkForce (freeform "0x7FFC00"); CBFS_SIZE = lib.mkForce (freeform "0x${lib.toHexString cbfs-size-in-bytes}");
COREBOOT_ROMSIZE_KB_16384 = lib.mkForce yes;
NO_POST = lib.mkForce yes; NO_POST = lib.mkForce yes;

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